# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv8.1m.main"

  define void @ne_trip_count(i1 zeroext %t1, ptr nocapture %a, ptr nocapture readonly %b, i32 %N) #0 {
  entry:
    %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
    br i1 %0, label %do.body.preheader, label %if.end

  do.body.preheader:                                ; preds = %entry
    %scevgep2 = getelementptr i32, ptr %a, i32 -1
    %scevgep5 = getelementptr i32, ptr %b, i32 -1
    br label %do.body

  do.body:                                          ; preds = %do.body, %do.body.preheader
    %lsr.iv6 = phi ptr [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ]
    %lsr.iv = phi ptr [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ]
    %1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ]
    %scevgep = getelementptr i32, ptr %lsr.iv6, i32 1
    %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 1
    %size = call i32 @llvm.arm.space(i32 4096, i32 undef)
    %tmp = load i32, ptr %scevgep, align 4
    store i32 %tmp, ptr %scevgep1, align 4
    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
    %3 = icmp ne i32 %2, 0
    %scevgep3 = getelementptr i32, ptr %lsr.iv, i32 1
    %scevgep7 = getelementptr i32, ptr %lsr.iv6, i32 1
    br i1 %3, label %do.body, label %if.end

  if.end:                                           ; preds = %do.body, %entry
    ret void
  }

  ; Function Attrs: nounwind
  declare i32 @llvm.arm.space(i32 immarg, i32) #1

  ; Function Attrs: noduplicate nounwind
  declare i1 @llvm.test.set.loop.iterations.i32(i32) #2

  ; Function Attrs: noduplicate nounwind
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2

  attributes #0 = { "target-features"="+lob" }
  attributes #1 = { nounwind }
  attributes #2 = { noduplicate nounwind }

...
---
name:            ne_trip_count
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: ne_trip_count
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
  ; CHECK:   liveins: $lr, $r1, $r2, $r3, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   dead $lr = t2SUBri $r3, 0, 14 /* CC::al */, $noreg, def $cpsr
  ; CHECK:   t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
  ; CHECK:   tB %bb.1, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.do.body.preheader:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r1, $r2, $r3
  ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.do.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1
  ; CHECK:   dead renamable $r2 = SPACE 4096, undef renamable $r0
  ; CHECK:   renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep)
  ; CHECK:   early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
  ; CHECK:   renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
  ; CHECK:   t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
  ; CHECK: bb.3.if.end:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.3(0x40000000)
    liveins: $r1, $r2, $r3, $r7, $lr

    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    $lr = t2WhileLoopStartLR $r3, %bb.3, implicit-def dead $cpsr
    tB %bb.1, 14, $noreg

  bb.1.do.body.preheader:
    successors: %bb.2(0x80000000)
    liveins: $r1, $r2, $r3

    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
    $lr = tMOVr killed $r3, 14, $noreg

  bb.2.do.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $r0, $r1

    dead renamable $r2 = SPACE 4096, undef renamable $r0
    renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load (s32) from %ir.scevgep)
    early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store (s32) into %ir.scevgep1)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.if.end:
    tPOP_RET 14, $noreg, def $r7, def $pc

...
